This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art.
Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request that a memory module retrieve data corresponding to the user input from its memory devices. In some instances, the retrieved data may include instructions executable by the processing circuitry to perform an operation and/or may include data to be used as an input for the operation. In addition, in some cases, data output from the operation may be stored in memory, for example, to enable subsequent retrieval.
The memory module may operate to retrieve or store data through commands that include addresses. These addresses correspond to locations in memory that are to be read from or written to as part of the operation. A row decoder may receive an address, interpret the address, and perform the requested operation to the data at the address. Furthermore, an address counter, such as a column before row address (CBR) counter, may maintain a count to facilitate tracking refresh operations of the memory module. During refresh operations, a normal word line is refreshed corresponding to the count maintained by the address counter. In certain refresh operations, redundant word lines are also to be refreshed using a count maintained separately from the count maintained by the described address counter. Thus, in these applications, utilizing a single address counter may be insufficient during refresh operations as two separate counts are to be maintained.